The present disclosure relates to methods for making field effect transistor devices and the resulting devices, and more specifically, to using delay elements with the back gate of such devices to reduce active power consumption.
Complementary metal oxide semiconductor (CMOS) logic dissipates less power than other logic circuits because CMOS dissipates power primarily only when switching (“dynamic power”). CMOS circuits are constructed in such a way that at least one P-type transistor and at least one N-type transistor are in series in any circuit path connecting relatively higher voltage (Vdd) to relatively lower voltage (Vss), and furthermore, at least one such N-type transistor or at least one P-type transistor in this path will have high resistance when not switching.
The composition of a P-type metal oxide semiconductor (PMOS) transistor creates low resistance between its source and drain contacts when a low gate voltage is applied and high resistance when a high gate voltage is applied. On the other hand, the composition of an N-type metal oxide semiconductor (NMOS) transistor creates high resistance between source and drain when a low gate voltage is applied and low resistance when a high gate voltage is applied.
CMOS circuits connect the drains and gates of the PMOS and NMOS transistors, typically connect the source of the PMOS to Vdd, and typically connect the source of the NMOS to Vss. Therefore, when the voltage of input (A) is low, the NMOS transistor's channel is off (in a high resistance state) preventing current flow from the output (Q) to ground; however, the PMOS transistor's channel is on (in a low resistance state) and current can flow from the Vdd to the output Q, and this causes the output Q to have high voltage (Vdd), the opposite of the input A. When the voltage of input A is high, the PMOS transistor is off, so no current flows from the Vdd to the output Q; however, the NMOS transistor is on, allowing the output to connect to ground Vss (again the inverse of the input A).
Therefore, CMOS accomplishes current reduction by complementing every N-type metal oxide semiconductor field effect transistor (nMOSFET) with a P-type metal oxide semiconductor field effect transistor (pMOSFET) and connecting both gates and both drains together. A high voltage on the gates will cause the nMOSFET to conduct and the pMOSFET to not conduct, while a low voltage on the gates causes the reverse.